The semiconductor industry continues to experience a need for higher levels of circuit integration. One approach to accomplish this goal involves scaling existing circuits such that smaller circuits are realized, thus allowing additional circuits to be integrated into a chip.
The scaling of integrated circuits to increase the packing density is accomplished by reducing the lateral dimensions of the transistor features. Generally, the various photolithographic masks are reduced in size so that the resulting circuits are also reduced in size. The scaling of P-channel (PMOS) insulated gate field effect transistors and N-channel (NMOS) transistors can be accomplished without substantial deterioration in performance, as the features of the transistors are laterally oriented at the face of the semiconductor body. While bipolar transistors can also be scaled to increase packing density, the lateral size of the device cannot be scaled as easily, as this family of devices is not a lateral-operating device, but rather depends upon the particular vertical spacing of semiconductor layers orthogonal to the face of the semiconductor body.
A major concern with scaling integrated circuits is the electrical isolation which must be maintained between the circuits. In other words, and unless otherwise desired, the electrical operation of one circuit must be independent of that of an adjacent circuit. One approach conventionally utilized for isolating circuits, especially of the bipolar type, is to form an N-type buried layer on a P-type substrate, and deposit a P-type epitaxial layer thereover. An N-well is formed in the epitaxial layer down and in contact with the buried layer. The base and emitter features of the bipolar transistor, as well as the collector contact, are formed in the N-well. The epitaxial layer surrounding the N-well is effective to isolate the bipolar transistor from adjacent circuits. This isolation technique is commonly referred to as the collector diffused isolation technology.
Another circuit isolation technique using the junction technology is commonly referred to as the standard buried collector technique. The standard buried collector technique is similar to the collector diffused isolation technique, but instead of forming a semiconductor well in the epitaxial layer, an annular P-type isolation ring is formed around an N epitaxial layer overlying the buried collector, thereby isolating the epitaxial well from adjacent circuits. The base, emitter and collector contact semiconductor regions are formed in the isolated epitaxial region.
Still another isolation technique involves the formation on an annular ring of a P-type semiconductor material surrounding and spaced apart from a buried collector. An epitaxial layer is deposited thereover, and a second P-type annular ring is formed in the epitaxial layer, overlying the bottom isolation ring. A thermal diffusing of the upper and bottom P-type isolation rings causes such rings to be joined, thereby encircling a portion of the epitaxial region and isolating it from adjacent circuits.
The disadvantage with such previously developed junction isolation techniques is that a substantial amount of lateral wafer area is required to form the isolation structures themselves. The wafer area problem encountered in utilizing junction-type isolation is further aggravated in fabricating high voltage bipolar transistors where the epitaxial layer is required to be relatively thick. In this situation, a diffused isolation region which extends from the face of the semiconductor body to the substrate also diffuses in the lateral direction to such an extent that appreciable wafer area is used. Moreover, a certain amount of "wasted" lateral area must be reserved between the isolation diffusions of adjacent circuits to prevent breakdown or "punch-through" between adjacent circuits. The wafer area required by the isolation diffusions and the wasted space may account for more than half the entire area of the circuit.
Another isolation technology conventionally employed in fabricating semiconductor circuits comprises an oxide isolation formed between circuits to be isolated. One technique utilizing oxide isolation includes masking circuit areas and selectively oxidizing through an epitaxial layer into an underlying substrate. Hence, adjacent circuits are electrically isolated by the silicon oxide. This technique is limited to the isolation of circuits formed in thin epitaxial layers. An uneven topographical surface may result when this method is attempted in conjunction with thicker epitaxial layers. In forming the isolation oxide with this technique, the oxide experiences a lateral spreading which encroaches on active circuit areas.
Another oxide isolation technique involves the formation of a deep trench anisotropically etched into the semiconductor material, and sloped etched at the upper trench corners to reduce the subsequent formation of crystal faults due to high temperature oxidation. A thin layer of silicon oxide is then formed on the trench sidewalls. A layer of silicon nitride is deposited on the trench sidewalls, and the trench is filled with polycrystalline silicon. Planarization of the wafer surface is required to form a topography suitable for subsequent masking, patterning and fabrication steps. This technique is disclosed in an article titled "Isolation Technique for High Speed Bipolar VLSI's", pp. 62-65, Vol. 82 IEEE Journal, 1982.
A major drawback associated with forming deep trenches is the damage to the silicon semiconductor material in regions adjacent the trench caused by subsequent annealing or heat treatment of the wafer, such as subsequent oxidation steps. The corners of the trench are known to be the mechanism for generating crystallographic dislocations and faults which extend substantial distances from the trench. Semiconductor circuits formed in the silicon material having these faults generally exhibit leaky PN junctions which severely deteriorate the performance of the circuit.
An additional drawback of oxide isolation in general is that there is no longer an electrically active medium from the surface to the underlying substrate. This shortcoming is often circumvented by providing a substrate contact on the backside thereof. Backside processing of the wafer requires special packaging techniques, including alloy mounting of a header to the chip.
For the foregoing, it can be seen that a need exists for a method and structure of isolating adjacent semiconductor circuits which may be shallow or deep, and which requires very little lateral wafer area. There is a concomitant need for a method of isolating adjacent circuits, while at the same time providing an electrical shield therebetween, as well as a surface contact to the underlying substrate.